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MPC603E7TEC/d (motorola order number) 1/1999 rev. 3.0 a this document contains information on a new product under development by motorola. motorola reserves the right to change or dis continue this product without notice. ? motorola inc., 1999. all rights reserved. technical data powerpc 603e a risc microprocessor family: pid7t-603e hardware specitcations the powerpc 603e microprocessor is an implementation of the powerpca family of reduced instruction set computing (risc) microprocessors. in this document, the term ?603e? is used as an abbreviation for ?powerpc 603e microprocessor?. the powerpc 603e microprocessors are available from motorola as mpc603e and from ibm as ppc603e. the 603e is implemented in several semiconductor fabrication processes. different processes may require different supply voltages and may have other electrical differences but will have the same functionality. as a technical designator to distinguish between 603e implementations in various processes, a pretx composed of the processor version register (pvr) value and a process identiter (pid) is assigned to the various implementations as shown below: powerpc 603e microprocessors from motorola technical designator process core voltage i/o voltage 5-volt tolerant part number pid6-603e 0.5 m cmos, 4lm 3.3 v 3.3 v yes mpc603e pid7v-603e 0.35 m cmos, 5lm 2.5 v 3.3 v yes mpc603p pid7t-603e 0.29 m cmos, 5lm 2.5 v 3.3 v yes mpc603r
2 pid7t-603e hardware specifications, rev. 3.0 motorola this document describes the pertinent physical characteristics of the pid7t-603e from motorola. for functional characteristics of the 603e, refer to the powerpc 603e risc microprocessor user?s manual . this document contains the following topics: topic page section 1.1, overview 2 section 1.2, features 3 section 1.3, general parameters 4 section 1.4, electrical and thermal characteristics 5 section 1.5, pin assignments 15 section 1.6, pinout listings 16 section 1.7, package descriptions 18 section 1.8, system design information 20 section 1.9, ordering information 27 to locate any published errata or updates for this document, refer to the website at http://www.motorola.com/powerpc/. 1.1 overview this section describes the features of the 603e and describes brie?y how those units interact. the 603e is a low-power implementation of the powerpc microprocessor family of reduced instruction set computing (risc) microprocessors. the 603e implements the 32-bit portion of the powerpc architecture specitcation, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and ?oating- point data types of 32 and 64 bits. for 64-bit powerpc microprocessors, the powerpc architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture. the 603e provides four software controllable power-saving modes. three of the modes (the nap, doze, and sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor. the fourth is a dynamic power management mode that causes the functional units in the 603e to automatically enter a low-power mode when the functional units are idle without affecting operational performance, software execution, or any external hardware. the 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock. instructions can execute out of order for increased performance; however, the 603e makes completion appear sequential. the 603e integrates tve execution units?an integer unit (iu), a ?oating-point unit (fpu), a branch processing unit (bpu), a load/store unit (lsu), and a system register unit (sru). the ability to execute tve instructions in parallel and the use of simple instructions with rapid execution times yield high eftciency and throughput for 603e-based systems. most integer instructions execute in one clock cycle. the fpu is pipelined so a single-precision multiply-add instruction can be issued every clock cycle. the 603e provides independent on-chip, 16-kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (mmus). the mmus contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (dtlb and itlb) that provide support for demand-paged virtual memory address translation and variable-sized block translation. the tlbs and caches use a least-recently used (lru) replacement algorithm. the 603e also supports block address translation through the use of two independent instruction and data block address translation (ibat and dbat) arrays of four entries each. effective addresses are compared simultaneously with all four entries in the bat array during block translation. in accordance with the powerpc architecture,
motorola pid7t-603e hardware specifications, rev. 3.0 3 if an effective address hits in both the tlb and bat array, the bat translation takes priority. the 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. the 603e interface protocol allows multiple masters to compete for system resources through a central external arbiter. the 603e provides a three-state coherency protocol that supports the exclusive, modited, and invalid cache states. this protocol is a compatible subset of the mesi (modited/exclusive/shared/invalid) four-state protocol and operates coherently in systems that contain four-state caches. the 603e supports single-beat and burst data transfers for memory accesses, and supports memory-mapped i/o. the 603e uses an advanced, 2.5/3.3-v cmos process technology and maintains full interface compatibility with ttl devices. 1.2 features this section summarizes features of the 603e?s implementation of the powerpc architecture. major features of the 603e are as follows: high-performance, superscalar microprocessor ? as many as three instructions issued and retired per clock ? as many as tve instructions in execution per clock ? single-cycle execution for most instructions ? pipelined fpu for all single-precision and most double-precision operations five independent execution units and two register tles ? bpu featuring static branch prediction ? a 32-bit iu ? fully ieee 754-compliant fpu for both single- and double-precision operations ? lsu for data transfer between data cache and gprs and fprs ? sru that executes condition register (cr), special-purpose register (spr) instructions, and integer add/compare instructions ? thirty-two gprs for integer operands ? thirty-two fprs for single- or double-precision operands high instruction and data throughput ? zero-cycle branch capability (branch folding) ? programmable static branch prediction on unresolved conditional branches ? instruction fetch unit capable of fetching two instructions per clock from the instruction cache ? a six-entry instruction queue that provides lookahead capability ? independent pipelines with feed-forwarding that reduces data dependencies in hardware ? 16-kbyte data cache?four-way set-associative, physically addressed; lru replacement algorithm ? 16-kbyte instruction cache?four-way set-associative, physically addressed; lru replacement algorithm ? cache write-back or write-through operation programmable on a per page or per block basis ? bpu that performs cr lookahead operations ? address translation facilities for 4-kbyte page size, variable block size, and 256-mbyte segment size
4 pid7t-603e hardware specifications, rev. 3.0 motorola ? a 64-entry, two-way set-associative itlb ? a 64-entry, two-way set-associative dtlb ? four-entry data and instruction bat arrays providing 128-kbyte to 256-mbyte blocks ? software table search operations and updates supported through fast trap mechanism ? 52-bit virtual address; 32-bit physical address facilities for enhanced system performance ? a 32- or 64-bit split-transaction external data bus with burst transfers ? support for one-level address pipelining and out-of-order bus transactions integrated power management ? low-power 2.5/3.3-volt design ? internal processor/bus clock multiplier that provides 2/1, 2.5/1, 3/1, 3.5/1, 4/1, 4.5/1, 5/1, 5.5/1, and 6/1 ratios ? three power saving modes: doze, nap, and sleep ? automatic dynamic power reduction when internal functional units are idle in-system testability and debugging features through jtag boundary-scan capability 1.3 general parameters the following list provides a summary of the general parameters of the pid7t-603e: technology 0.29 m cmos, tve-layer metal die size 5.65 mm x 7.7 mm (44 mm 2 ) transistor count 2.6 million logic design fully-static package 255 ceramic ball grid array (cbga) core power supply 2.5 5% v dc i/o power supply 3.3 5% v dc
motorola pid7t-603e hardware specifications, rev. 3.0 5 1.4 electrical and thermal characteristics this section provides the ac and dc electrical specitcations and thermal characteristics for the pid7t- 603e. 1.4.1 dc electrical characteristics the tables in this section describe the pid7t-603e dc electrical characteristics. table 1 provides the absolute maximum ratings. table 2 provides the recommended operating conditions for the pid7t-603e. table 1. absolute maximum ratings characteristic symbol value unit core supply voltage vdd e0.3 to 2.75 v pll supply voltage avdd e0.3 to 2.75 v i/o supply voltage ovdd e0.3 to 3.6 v input voltage v in e0.3 to 5.5 v storage temperature range t stg e55 to 150 ?c notes : 1. functional and tested operating conditions are given in table 2. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution : v in must not exceed ovdd by more than 2.5 v at any time, including during power-on reset. 3. caution : ovdd must not exceed vdd/avdd by more than 1.2 v at any time, including during power-on reset. 4. caution : vdd/avdd must not exceed ovdd by more than 0.4 v at any time, including during power-on reset. table 2. recommended operating conditions characteristic symbol value unit core supply voltage vdd 2.375 to 2.625 v pll supply voltage avdd 2.375 to 2.625 v i/o supply voltage ovdd 3.135 to 3.465 v input voltage v in gnd to 5.5 v die-junction temperature tj 0 to 105 ?c note: these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed.
6 pid7t-603e hardware specifications, rev. 3.0 motorola table 3 provides the package thermal characteristics for the pid7t-603e. table 4 provides the dc electrical characteristics for the pid7t-603e. table 3. package thermal characteristics characteristic symbol value rating cbga package die junction-to-case thermal resistance (typical) q jc 0.095 ?c/w cbga package die junction-to-ball thermal resistance (typical) q jb 3.5 ?c/w note: refer to section 1.8, system design information, for more details about thermal management. table 4. dc electrical specifications vdd = avdd = 2.5 5% v dc, ovdd = 3.3 5% v dc, gnd = 0 v dc, 0 tj 105 ?c characteristic symbol min max unit notes input high voltage (all inputs except sysclk) v ih 2.0 5.5 v input low voltage (all inputs except sysclk) v il gnd 0.8 v sysclk input high voltage cv ih 2.4 5.5 v sysclk input low voltage cv il gnd 0.4 v input leakage current, v in = 3.465 v i in ? 30 a 1,2 v in = 5.5 v i in ? 300 a 1,2 hi-z (off-state) leakage current, v in = 3.465 v i tsi ? 30 a 1,2 v in = 5.5 v i tsi ? 300 a 1,2 output high voltage, i oh = e7 ma v oh 2.4 ? v output low voltage, i ol = 7 ma v ol ? 0.4 v capacitance, v in = 0 v, f = 1 mhz (excludes ts , abb , dbb , and ar tr y ) c in ? 10.0 pf 3 capacitance, v in = 0 v, f = 1 mhz (for ts , abb , dbb , and ar tr y )c in ? 15.0 pf 3 notes : 1. excludes test signals (lssd_mode, l1_tstclk, l2_tstclk, and jtag signals). 2. the leakage is measured for nominal ovdd and vdd or both ovdd and vdd must vary in the same direction (for example, both ovdd and vdd vary by either +5% or -5%). 3. capacitance is periodically sampled rather than 100% tested.
motorola pid7t-603e hardware specifications, rev. 3.0 7 table 5 provides the power consumption for the pid7t-603e. 1.4.2 ac electrical characteristics this section provides the ac electrical characteristics for the pid7t-603e. these specitcations are for 200, 266 and 300 mhz processor speed grades. the processor core frequency is determined by the bus (sysclk) frequency and the settings of the pll_cfg[0e3] signals. all timings are specited respective to the rising edge of sysclk. pll_cfg signals should be set prior to power up and not altered afterwards. 1.4.2.1 clock ac specitcations table 6 provides the clock ac timing specitcations as detned in figure 1. after fabrication, parts are sorted by maximum processor core frequency as shown in section 1.4.2.1, clock ac specitcations, and tested for conformance to the ac specitcations for that frequency. parts are sold by maximum processor core frequency; see section 1.9, ordering information. table 5. power consumption processor (cpu) frequency unit 100 mhz 133 mhz 166 mhz 200 mhz 233 mhz 266 mhz 300 mhz full-on mode (dpm enabled) typical 1.1 1.6 2.1 2.5 3.0 3.5 4.0 w maximum 1.6 2.4 3.2 4.0 4.6 5.3 6.0 w doze mode typical 0.55 .7 .9 1.1 1.3 1.5 1.8 w nap mode typical 50 60 75 85 100 120 130 mw sleep mode typical 45 50 55 65 75 90 100 mw sleep mode?pll disabled typical 40 40 40 40 40 40 40 mw sleep mode?pll and sysclk disabled typical 15 15 15 15 15 15 15 mw maximum 25 25 25 25 25 80 100 mw notes : 1. these values apply for all valid pll_cfg[0e3] settings and do not include output driver power (ovdd) or analog supply power (avdd). ovdd power is system dependent but is typically 10% of vdd. worst-case avdd = 15 mw. 2. typical power is an average value measured at vdd = avdd = 2.5 v, ovdd = 3.3v, in a system executing typical applications and benchmark sequences. 3. maximum power is measured at 2.625 v using a worst-case instruction mix.
8 pid7t-603e hardware specifications, rev. 3.0 motorola table 6. clock ac timing specifications vdd = avdd = 2.5 5% v dc, ovdd = 3.3 5% v dc, gnd = 0 v dc , 0 tj 105 ?c num characteristic 200 mhz 266 mhz 300 mhz unit notes min max min max min max processor frequency 80 200 150 266 180 300 mhz 1,6 vco frequency 300 400 300 532 360 600 mhz 1 sysclk frequency 25 66.67 25 75 33.3 75 mhz 1 1 sysclk cycle time 13.3 40 13.3 40 13.3 30 ns 2,3 sysclk rise and fall time ? 2.0 ? 2.0 ? 2.0 ns 2 4 sysclk duty cycle measured at 1.4 v 40.0 60.0 40.0 60.0 40.0 60.0 % 3 sysclk jitter ? 150 ? 150 ? 150 ps 4 pid7t internal pll-relock time ? 100 ? 100 ? 100 m s 3,5 notes : 1. caution : the sysclk frequency and pll_cfg[0e3] settings must be chosen such that the resulting sysclk (bus) frequency, cpu (core) frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0e3] signal description in section 1.8, system design information, for valid pll_cfg[0e3] settings. 2. rise and fall times for the sysclk input are measured from 0.4 v to 2.4 v. 3. timing is guaranteed by design and characterization, and is not tested. 4. cycle-to-cycle jitter, and is guaranteed by design. the total input jitter (short term and long term combined) must be under 150 ps to guarantee the input/output timing of section 1.4.2.2, input ac specitcations, and section 1.4.2.3, output ac specitcations. 5. relock timing is guaranteed by design and characterization, and is not tested. pll-relock time is the maximum time required for pll lock after a stable vdd, ovdd, avdd, and sysclk are reached during the power-on reset sequence. this specitcation also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time (100 m s) during the power-on reset sequence. 6. operation below 150 mhz is supported only by pll_cfg[0e3] = 0b0101. refer to section 1.8.1, pll contguration for additional information.
motorola pid7t-603e hardware specifications, rev. 3.0 9 figure 1 provides the sysclk input timing diagram. figure 1. sysclk input timing diagram 1.4.2.2 input ac specitcations table 7 provides the input ac timing specitcations for the pid7t-603e as detned in figure 2 and figure 3. table 7. input ac timing specifications 1 vdd = avdd = 2.5 5% v dc, ovdd = 3.3 5% v dc, gnd = 0 v dc , 0 tj 105? c num characteristic 200, 266, 300 mhz unit notes min max 10a address/data/transfer attribute inputs valid to sysclk (input setup) 2.5 ? ns 2 10b all other inputs valid to sysclk (input setup) 3.5 ? ns 3 10c mode select inputs valid to hreset (input setup) (for dr tr y , qa ck and tlbisync ) 8?t sysclk 4, 5, 6, 7 11a sysclk to address/data/transfer attribute inputs invalid (input hold) 1.0 ? ns 2 11b sysclk to all other inputs invalid (input hold) 1.0 ? ns 3 11c hreset to mode select inputs invalid (input hold) (for dr tr y , qa ck , and tlbisync ) 0 ? ns 4, 6, 7 note s: 1. input specitcations are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the 1.4 v of the rising edge of the input sysclk. input and output timings are measured at the pin. 2. address/data/transfer attribute input signals are composed of the following?a[0e31], ap[0e3], tt[0e4], tc[0e1], tbst , tsiz[0e2], gbl , dh[0e31], dl[0e31], dp[0e7]. 3. all other input signals are composed of the following?ts , abb , dbb , ar tr y , bg , aa ck , dbg , dbw o , t a , dr tr y , tea , dbdis , hreset , sreset , int , smi , mcp , tben, qa ck , tlbisync . 4. the setup and hold time is with respect to the rising edge of hreset (see figure 3). 5. t sysclk is the period of the external clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 6. these values are guaranteed by design, and are not tested. 7. this specitcation is for contguration mode only. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. vm cvil cvih sysclk 2 3 4 vm = midpoint voltage (1.4 v) 4 1 vm vm
10 pid7t-603e hardware specifications, rev. 3.0 motorola figure 2 provides the input timing diagram for the pid7t-603e . figure 2. input timing diagram figure 3 provides the mode select input timing diagram for the pid7t-603e. figure 3. mode select input timing diagram 1.4.2.3 output ac specitcations table 8 provides the output ac timing specitcations for the pid7t-603e as detned in figure 4. table 8. output ac timing specifications 1 vdd = avdd = 2.5 5% v dc, ovdd = 3.3 5%, gnd = 0 v dc, 0 tj 105 ?c, c l = 50 pf (unless otherwise noted) num characteristic 200, 266, 300 mhz unit notes min max 12 sysclk to output driven (output enable time) 1.0 ? ns 13a sysclk to output valid (5.5 v to 0.8 v?ts , abb , ar tr y , dbb ) ? 9.0 ns 3 13b sysclk to output valid (ts , abb , ar tr y , dbb ) ? 8.0 ns 5 14a sysclk to output valid (5.5 v to 0.8 v?all except ts , abb , ar tr y , dbb ) ? 11.0 ns 3 vm sysclk all inputs vm = midpoint voltage (1.4 v) 10a 10b 11a 11b mode pins hreset 10c 11c vm = midpoint voltage (1.4 v) vm
motorola pid7t-603e hardware specifications, rev. 3.0 11 14b sysclk to output valid (all except ts , abb , ar tr y , dbb ) ? 9.0 ns 5 15 sysclk to output invalid (output hold) 1.0 ? ns 2 16 sysclk to output high impedance (all except ar tr y , abb , dbb ) ? 8.0 ns 17 sysclk to abb , dbb , high impedance after precharge ? 1.0 t sysclk 4, 6 18 sysclk to ar tr y high impedance before precharge ? 7.5 ns 19 sysclk to ar tr y precharge enable 0.2 * t sysclk + 1.0 ? ns 2, 4, 7 20 maximum delay to ar tr y precharge ? 1.0 t sysclk 4, 7 21 sysclk to ar tr y high impedance after precharge ? 2.0 t sysclk 5,7 notes : 1. all output specitcations are measured from the 1.4 v of the rising edge of sysclk to the ttl level (0.8 v or 2.0 v) of the signal in question. both input and output timings are measured at the pin (see figure 4). 2. this minimum parameter assumes c l = 0 pf. 3. sysclk to output valid (5.5 v to 0.8 v) includes the extra delay associated with discharging the external voltage from 5.5 v to 0.8 v instead of from vdd to 0.8 v (5-v cmos levels instead of 3.3-v cmos levels). 4. t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 5. output signal transitions from gnd to 2.0 v or vdd to 0.8 v. 6. nominal precharge width for abb and dbb is 0.5 t sysclk . 7. nominal precharge width for ar tr y is 1.0 t sysclk . table 8. output ac timing specifications 1 (continued) vdd = avdd = 2.5 5% v dc, ovdd = 3.3 5%, gnd = 0 v dc, 0 tj 105 ?c, c l = 50 pf (unless otherwise noted) num characteristic 200, 266, 300 mhz unit notes min max
12 pid7t-603e hardware specifications, rev. 3.0 motorola figure 4 provides the output timing diagram for the pid7t-603e. figure 4. output timing diagram sysclk 12 14 13 15 16 ts ar tr y abb , dbb vm vm vm = midpoint voltage (1.4 v) vm 13 20 18 17 21 19 15 16 all outputs (except ts , abb , dbb , artry )
motorola pid7t-603e hardware specifications, rev. 3.0 13 1.4.3 jtag ac timing specitcations table 9 provides the jtag ac timing specitcations as detned in figure 5, figure 6, figure 7 and figure 8. figure 5 provides the jtag clock input timing diagram. figure 5. jtag clock input timing diagram table 9. jtag ac timing specifications vdd = avdd = 2.5 5% v dc, ovdd = 3.3 5%, gnd = 0 v dc, 0 tj 105? c, c l = 50 pf num characteristic min max unit notes tck frequency of operation 0 16 mhz 1 tck cycle time 62.5 ? ns 2 tck clock pulse width measured at 1.4 v 25 ? ns 3 tck rise and fall times 0 3 ns 4 trst setup time to tck rising edge 13 ? ns 1 5 trst assert time 40 ? ns 6 boundary scan input data setup time 6 ? ns 2 7 boundary scan input data hold time 27 ? ns 2 8 tck to output data valid 4 25 ns 3 9 tck to output high impedance 3 24 ns 3 10 tms, tdi data setup time 0 ? ns 11 tms, tdi data hold time 25 ? ns 12 tck to tdo data valid 4 24 ns 13 tck to tdo high impedance 3 15 ns notes : 1. trst is an asynchronous signal. the setup time is for test purposes only. 2. non-test signal input timing with respect to tck. 3. non-test signal output timing with respect to tck. tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage (1.4 v)
14 pid7t-603e hardware specifications, rev. 3.0 motorola figure 6 provides the trst timing diagram . figure 6. trst timing diagram figure 7 provides the boundary-scan timing diagram. figure 7. boundary-scan timing diagram figure 8 provides the test access port timing diagram. figure 8. test access port timing diagram 4 5 trst tck vm input data valid output data valid output data valid tck data inputs data outputs data outputs data outputs 6 7 8 8 9 vm vm input data valid output data valid output data valid tck tdi, tms tdo tdo tdo 10 11 12 12 13 vm vm
motorola pid7t-603e hardware specifications, rev. 3.0 15 1.5 pin assignments figure 9 (in part a) shows the pinout of the cbga package as viewed from the top surface. part b shows the side profile of the cbga package to indicate the direction of the top surface view. part a figure 9. pinout of the cbga package as viewed from the top surface a b c d e f g h j k l m n p r t 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 not to scale part b substrate assembly encapsulant view die
16 pid7t-603e hardware specifications, rev. 3.0 motorola 1.6 pinout listings table 10 provides the pinout listing for the 603e cbga package. table 10. pinout listing for the 255-pin cbga package signal name pin number active i/o a[0e31] c16, e04, d13, f02, d14, g01, d15, e02, d16, d04, e13, go2, e15, h01, e16, h02, f13, j01, f14, j02, f15, h03, f16, f04, g13, k01, g15, k02, h16, m01, j15, p01 high i/o aa ck l02 low input abb k04 low i/o ap[0e3] c01, b04, b03, b02 high i/o ape a04 low output ar tr y j04 low i/o avdd a10 ? ? bg l01 low input br b06 low output ci e01 low output ckstp_in d08 low input ckstp_out a06 low output clk_out d07 ? output cse[0e1] b01, b05 high output dbb j14 low i/o dbg n01 low input dbdis h15 low input dbw o g04 low input dh[0e31] p14, t16, r15, t15, r13, r12, p11, n11, r11,t12, t11, r10, p09, n09, t10, r09, t09, p08, n08, r08, t08, n07, r07, t07, p06, n06, r06, t06, r05, n05, t05, t04 high i/o dl[0e31] k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n16, n15, n13, n14, p16, p15, r16, r14, t14, n10, p13, n12, t13, p03, n03, n04, r03, t01, t02, p04, t03, r04 high i/o dp[0e7] m02, l03, n02, l04, r01, p02, m04, r02 high i/o dpe a05 low output dr tr y g16 low input gbl f01 low i/o gnd c05, c12, e03, e06, e08, e09, e11, e14, f05, f07, f10, f12, g06, g08, g09, g11, h05, h07, h10, h12, j05, j07, j10, j12, k06, k08, k09, k11, l05, l07, l10, l12, m03, m06, m08, m09, m11, m14, p05, p12 ??
motorola pid7t-603e hardware specifications, rev. 3.0 17 hreset a07 low input int b15 low input l1_tstclk 1 d11 ? input l2_tstclk 1 d12 ? input lssd_mode 1 b10 low input mcp c13 low input nc (no-connect) b07, b08, c03, c06, c08, d05, d06, h04, j16 ? ? ovdd c07, e05, e07, e10, e12, g03, g05, g12, g14, k03, k05, k12, k14, m05, m07, m10, m12, p07, p10 ?? pll_cfg[0e3] a08, b09, a09, d09 high input qa ck d03 low input qreq j03 low output rsrv d01 low output smi a16 low input sreset b14 low input sysclk c09 ? input t a h14 low input tben c02 high input tbst a14 low i/o tc[0e1] a02, a03 high output tck c11 ? input tdi a11 high input tdo a12 high output tea h13 low input tlbisync c04 low input tms b11 high input trst c10 low input ts j13 low i/o tsiz[0e2] a13, d10, b12 high output tt[0e4] b13, a15, b16, c14, c15 high i/o table 10. pinout listing for the 255-pin cbga package (continued) signal name pin number active i/o
18 pid7t-603e hardware specifications, rev. 3.0 motorola 1.7 package descriptions the following sections provide the package parameters and the mechanical dimensions for the 603e. note that the pid7t-603e is currently offered only in the ceramic ball grid array (cbga) package. 1.7.1 cbga package description the following sections provide the package parameters and mechanical dimensions for the cbga package. 1.7.1.1 package parameters the package parameters are as provided in the following list. the package type is 21 mm x 21 mm, 255- lead ceramic ball grid array (cbga). package outline 21 mm x 21 mm interconnects 255 pitch 1.27 mm (50 mil) package height minimum: 2.45 mm maximum: 3.00 mm ball diameter 0.89 mm (35 mil) maximum heat sink force 10 lbs wt d02 low output vdd 2 f06, f08, f09, f11, g07, g10, h06, h08, h09, h11, j06, j08, j09, j11, k07, k10, l06, l08, l09, l11 ?? voltdetgnd 3 f03 low output notes: 1. these are test signals for factory use only and must be pulled up to ovdd for normal machine operation. 2. ovdd inputs supply power to the i/o drivers and vdd inputs supply power to the processor core. 3. nc (no-connect) in the pid6-603e; internally tied to gnd in the pid7v-603e and pid7t-603e cbga package to indicate to the power supply that a low-voltage processor is present. table 10. pinout listing for the 255-pin cbga package (continued) signal name pin number active i/o
motorola pid7t-603e hardware specifications, rev. 3.0 19 1.7.1.2 mechanical dimensions of the cbga package figure 10 provides the mechanical dimensions and bottom surface nomenclature of the cbga package. figure 10. mechanical dimensions and bottom surface nomenclature of the cbga package notes: 1. dimensioning and tolerancing per ansi y14.5 m 1982. 2. controlling dimension: millimeter. 0.200 f t 255x a 2x a1 corner p n 0.200 2x e e e 12345678910111213141516 a b c d e f g h j k l m n p r t e 0.300 t 0.150 d c h 0.150 t b e f e k k g s s s s e t e dim millimeters inches min max min max a 21.000 bsc 0.827 bsc b 21.000 bsc 0.827 bsc c 2.450 3.000 0.097 0.118 d 0.820 0.930 0.032 0.036 g 1.270 bsc 0.050 bsc h 0.790 0.990 0.031 0.039 k 0.635 bsc 0.025 bsc n 5.000 16.000 0.197 0.630 p 5.000 16.000 0.197 0.630
20 pid7t-603e hardware specifications, rev. 3.0 motorola 1.8 system design information this section provides electrical and thermal design recommendations for successful application of the 603e. 1.8.1 pll contguration the 603e pll is contgured by the pll_cfg[0e3] signals. for a given sysclk (bus) frequency, the pll contguration signals set the internal cpu and vco frequency of operation. the pll contguration for the pid7t-603e is shown in table 11 for nominal frequencies. table 11. pll configuration pll_cfg[0e3] cpu frequency in mhz (vco frequency in mhz) bus-to- core multiplier core-to vco multiplier bus 25 mhz bus 33.33 mhz bus 40 mhz bus 50 mhz bus 60 mhz bus 66.67 mhz bus 75 mhz 0100 2x 2x ? ? ????150 (300) 0101 2x 4x ? ? 80 (320) 100 (400) 120 (480) 133 (532) 150 (600) 0110 2.5x 2x ? ? ? ? 150 (300) 166 (333) 187 (375) 1000 3x 2x ? ? ? 150 (300) 180 (360) 200 (400) 225 (450) 1110 3.5x 2x ? ? ? 175 (350) 210 (420) 233 (466) 263 (525) 1010 4x 2x ? ? 160 (320) 200 (400) 240 (480) 267 (533) 300 (600) 0111 4.5x 2x ? 150 (300) 180 (360) 225 (450) 270 (540) 300 (600) ? 1011 5x 2x ? 166 (333) 200 (400) 250 (500) 300 (600) ?? 1001 5.5x 2x ? 183 (366) 220 (440) 275 (550) ??? 1101 6x 2x 150 (300) 200 (400) 240 (480) 300 (600) ??? 0011 pll bypass 1111 clock off notes : 1. some pll contgurations may select bus, cpu, or vco frequencies which are not supported; see section 1.4.2.1, clock ac specitcations, for valid sysclk and vco frequencies. 2. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. note : the ac timing specitcations given in this document do not apply in pll-bypass mode. 3. in clock-off mode, no clocking occurs inside the 603e regardless of the sysclk input.
motorola pid7t-603e hardware specifications, rev. 3.0 21 1.8.2 pll power supply filtering the avdd power signal is provided on the 603e to provide power to the clock generation phase-locked loop. to ensure stability of the internal clock, the power supplied to the avdd input signal should be tltered using a circuit similar to the one shown in figure 11. the circuit should be placed as close as possible to the avdd pin to ensure it tlters out as much noise as possible. the 0.1 f capacitor should be closest to the avdd pin, followed by the 10 f capacitor, and tnally the 10 w resistor to vdd. these traces should be kept short and direct. figure 11. pll power supply filter circuit 1.8.3 decoupling recommendations due to the 603e?s dynamic power management feature, large address and data buses, and high operating frequencies, the 603e can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the 603e system, and the 603e itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each vdd and ovdd pin of the 603e. it is also recommended that these decoupling capacitors receive their power from separate vdd, ovdd, and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should vary in value from 220 pf to 10 m f to provide both high- and low-frequency tltering, and should be placed as close as possible to their associated vdd or ovdd pin. suggested values for the vdd pins?220 pf (ceramic), 0.01 f (ceramic), and 0.1 f (ceramic). suggested values for the ovdd pins?0.01 f (ceramic), 0.1 f (ceramic), and 10 f (tantalum). only smt (surface mount technology) capacitors should be used to minimize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the vdd and ovdd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should also have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100 f (avx tps tantalum) or 330 f (avx tps tantalum). 1.8.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to vdd. unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external vdd, ovdd, and gnd pins of the 603e. 1.8.5 pull-up resistor requirements the 603e requires high-resistive (weak: 10 k w ) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the 603e or other bus master. these signals are?ts , abb , dbb , and ar tr y . vdd avdd 10 w 10 f 0 . 1 f gnd
22 pid7t-603e hardware specifications, rev. 3.0 motorola in addition, the 603e has three open-drain style outputs that require pull-up resistors (weak or stronger: 4.7 k w e10 k w ) if they are used by the system. these signals are?ape , dpe , and ckstp_out . during inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may ?oat in the high-impedance state for relatively long periods of time. since the 603e must continually monitor these signals for snooping, this ?oat condition may cause excessive power draw by the input receivers on the 603e. it is recommended that these signals be pulled up through weak (10 k w ) pull- up resistors or restored in some manner by the system. the snooped address and transfer attribute inputs are?a[0e31], ap[0e3], tt[0e4], tbst , and gbl . the data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. 1.8.6 thermal management information this section provides thermal management information for the ceramic ball grid array (cbga) package for air-cooled applications. proper thermal control design is primarily dependent upon the system-level design?the heat sink, air?ow and thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods?adhesive, spring clip to holes in the printed- circuit board or package, and mounting clip and screw assembly (cbga package); see figure 12. this spring force should not exceed 5.5 pounds of force. figure 12. package exploded cross-sectional view with several heat sink options adhesive or thermal interface material heat sink cbga package heat sink clip printed-circuit board option
motorola pid7t-603e hardware specifications, rev. 3.0 23 the board designer can choose between several types of heat sinks to place on the 603e. there are several commercially-available heat sinks for the 603e provided by the following vendors: chip coolers inc. 800-227-0254 (usa/canada) 333 strawberry field rd. 401-739-7600 warwick, ri 02887-6979 international electronic research corporation (ierc) 818-842-7277 135 w. magnolia blvd. burbank, ca 91502 thermalloy 214-243-4321 2021 w. valley view lane p.o. box 810839 dallas, tx 75731 waketeld engineering 617-245-5900 60 audubon rd. waketeld, ma 01880 aavid engineering 603-528-3400 one kool path laconia, nh 03247-0440 ultimately, the tnal selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 1.8.6.1 internal package conduction resistance for this packaging technology the intrinsic thermal conduction resistance (shown in table 3) versus the external thermal resistance paths are shown in figure 13 for a package with an attached heat sink mounted to a printed-circuit board. figure 13. package with heat sink mounted to a printed-circuit board external resistance external resistance internal resistance (note the internal versus external package resistance) radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package
24 pid7t-603e hardware specifications, rev. 3.0 motorola 1.8.6.2 adhesives and thermal interface materials a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 14 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/ oil, ?oroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease signitcantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 12). this spring force should not exceed 5.5 pounds of force. therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. of course, the selection of any thermal interface material depends on many factors?thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. figure 14. thermal performance of select thermal interface material 0 0.5 1 1.5 2 0 1020304050607080 silicone sheet (0.006 inch) bare joint floroether oil sheet (0.007 inch) graphite/oil sheet (0.005 inch) synthetic grease contact pressure (psi) specific thermal resistance (kin 2 /w)
motorola pid7t-603e hardware specifications, rev. 3.0 25 the board designer can choose between several types of thermal interface. heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. there are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: dow-corning corporation 517-496-4000 dow-corning electronic materials po box 0997 midland, mi 48686-0997 chomerics, inc. 617-935-4850 77 dragon court woburn, ma 01888-4850 thermagon inc. 216-741-7659 3256 west 25th street cleveland, oh 44109-1668 loctite corporation 860-571-5100 1001 trout brook crossing rocky hill, ct 06067 ai technology (e.g. eg7655) 609-882-2332 1425 lower ferry rd trent, nj 08618 the following section provides a heat sink selection example using one of the commercially available heat sinks. 1.8.6.3 heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t a + t r + ( q jc + q int + q sa ) * p d where : t j is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet q jc is the die junction-to-case thermal resistance q int is the adhesive or interface material thermal resistance q sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation the die-junction temperatures (t j ) should be maintained less than the value specited in table 2. the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40 ?c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 ?c. the thermal resistance of the thermal interface material ( q int ) is typically about 1 ?c/ w. assuming a t a of 30 ?c, a t r of 5 ?c a cbga package q jc = 0.095 , and a power consumption (p d ) of 3.0 watts, the following expression for t j is obtained: die-junction temperature: t j = 30 ?c + 5 ?c + (0.095 ?c/w + 1.0 ?c/w + r sa ) * 3.0 w
26 pid7t-603e hardware specifications, rev. 3.0 motorola for a thermalloy heat sink #2328b, the heat sink-to-ambient thermal resistance (r sa ) versus air?ow velocity is shown in figure 15. figure 15. thermalloy #2328b heat sink-to-ambient thermal resistance versus airflow velocity assuming an air velocity of 0.5 m/s, we have an effective r sa of 7 ?c/w, thus t j = 30?c + 5?c + (0.095 ?c/w +1.0 ?c/w + 7 ?c/w) * 3.0 w, resulting in a die-junction temperature of approximately 60 ?c which is well within the maximum operating temperature of the component. other heat sinks offered by chip coolers, ierc, thermalloy, waketeld engineering, and aavid engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air ?ow. though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common tgure- of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat ?ow. the tnal die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the tnal operating die-junction temperature?air?ow, board population (local heat ?ux of adjacent components), heat sink eftciency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. to expedite system-level thermal analysis, several compact thermal-package models are available within flotherm. these are available upon request. 1 3 5 7 8 0 0.5 1 1.5 2 2.5 3 3.5 thermalloy #2328b pin-fin heat sink approach air velocity (m/s) heat sink thermal resistance (?c/w) (25 x28 x 15 mm) 2 4 6
motorola pid7t-603e hardware specifications, rev. 3.0 27 1.9 ordering information figure 16 provides the part numbering nomenclature for the pid7t-603e. note that the individual part numbers correspond to a maximum processor core frequency. for available frequencies, contact your local motorola sales oftce. in addition to the processor frequency, the part numbering scheme also consists of a part moditer and application moditer. the part moditer indicates any enhancement(s) in the part from the original design. the application moditer may specify special bus frequencies or application conditions. each part number also contains a revision code. this refers to the die mask revision number and is specited in the part numbering scheme for identitcation purposes only. figure 16part number key mpc 603 r rx xxx x x product code part identifier part modifier application modifier (r = remapped, enhanced, low-voltage) (l = any valid pll configuration) package processor frequency (contact motorola sales office) revision level (rx = cbga without lid) (t = extended termperature range)
mfax is a trademark of motorola, inc. the powerpc name, the powerpc logotype, and powerpc 603e are trademarks of international busines machines corporation, used by motorola under license from international business machines corporation. flotherm is a registered trademark of flomerics ltd., uk. information in this document is provided solely to enable system and software implementers to use powerpc microprocessors. ther e are no express or implied copyright licenses granted hereunder to design or fabricate powerpc integrated circuits or integrated circuits based on the inf ormation in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. t ypical parameters can and do vary in different applications. all operating parameters, including typicals must be validated for each customer application by custo mer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any o ther application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorol a products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affi liates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any clai m of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the desig n or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/aftrmative action employer. motorola literature distribution centers : usa/europe: motorola literature distribution; p.o. box 5405; denver, colorado 80217; tel.: 1-800-441-2447 or 1-303-675-2140; world wide web address: http://ldc.nmd.com/ japan : nippon motorola ltd spd, strategic planning office 4-32-1, nishi-gotanda shinagawa-ku, tokyo 141, japan tel.: 81-3-5487-8488 asia/pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong; tel.: 852-26629298 mfaxa : rmfax0@email.sps.mot.com; touchtone 1-602-244-6609; us & canada only (800) 774-1848; world wide web address : http://sps.motorola.com/mfax internet : http://motorola.com/sps technical information : motorola inc. sps customer support center 1-800-521-6274; electronic mail address: crc@wmkmail.sps.mot.com. document comments : fax (512) 895-2638, attn: risc applications engineering. world wide web addresses : http://www.motorola.com/powerpc/ http://www.motorola.com/netcomm/ MPC603E7TEC/d

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